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Concurrent Double Level Wiring Process

IP.com Disclosure Number: IPCOM000035853D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28

Publishing Venue

IBM

Related People

Authors:
Cronin, JE Kaanta, CW [+details]

Abstract

Two levels of wiring are formed in an insulator stack by means of two mask areas passing two levels of light flux to expose a single photoresist and use of etch stop (ES) layers in the insulator stack. Improved wiring density is obtained from resultant improved planarization and, when a single gray level mask is used for definition of the two wiring levels, a further wiring density improvement is obtained. (Image Omitted)