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Cyclic Redundancy Check Control Subsystem for the Functional Self-Test Chip (Fstc) Prototype

IP.com Disclosure Number: IPCOM000035856D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28

Publishing Venue

IBM

Related People

Authors:
Chan, GK O'Dell, JT Valashinas, DA [+details]

Abstract

The control system described in this article serves to control the cyclic redundancy check (CRC) data acquisition, data compression, and signature read modes designed for the functional self-test chip (FSTC) prototype.