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Borderless Gate Contacts for CMOS Applications

IP.com Disclosure Number: IPCOM000035904D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28

Publishing Venue

IBM

Related People

Authors:
Bajuk, S Bhattacharyya, A Combes, M Mann, R Mollier, P Rivier, M [+details]

Abstract

As the gate count increases and the device size decreases in CMOS VLSI logic chips, the wiring contribution to the overall chip performance becomes more and more important. This is especially true in gate arrays where wiring constraints are the largest. A huge development effort is aimed at the minimization of wiring length through improved process (reduced metal pitch, three-level metallization) and improved placement and wiring algorithms.