Borderless Gate Contacts for CMOS Applications
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
As the gate count increases and the device size decreases in CMOS VLSI logic chips, the wiring contribution to the overall chip performance becomes more and more important. This is especially true in gate arrays where wiring constraints are the largest. A huge development effort is aimed at the minimization of wiring length through improved process (reduced metal pitch, three-level metallization) and improved placement and wiring algorithms.