Browse Prior Art Database

CMOS PROCESSES WITH LOW RESISTANCE p- AND n-DOPED GATES

IP.com Disclosure Number: IPCOM000035930D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28

Publishing Venue

IBM

Related People

Authors:
Davari, B Dennard, RH Taur, Y Moy, D [+details]

Abstract

This article describes a process and an alternative which can give a relatively thin silicide layer over all junction areas of a complementary metal-oxide semiconductor (CMOS) transistor while giving a relatively thick, low resistance layer over the gate areas. These processes also allow the gates of p- and n-channel devices to be doped p+ and n+, respectively, by the source/drain implant steps.