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64-Bit Structured Partial Decoded Shifter Circuit

IP.com Disclosure Number: IPCOM000035932D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28

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Desrosiers, B Steimle, A [+details]


The principle of this shifter circuit lies on the separation of the 64 bits into eight groups of eight bits each. Shift is performed in going through the two stages of the shifter: Stage 1 : Shifts 0 to 7 groups of 8 bits Stage 2 : Shifts 0 to 7 bits