Dismiss
The InnovationQ application will be updated on Sunday, May 31st from 10am-noon ET. You may experience brief service interruptions during that time.
Browse Prior Art Database

64-Bit Structured Partial Decoded Shifter Circuit

IP.com Disclosure Number: IPCOM000035932D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28

Publishing Venue

IBM

Related People

Authors:
Desrosiers, B Steimle, A [+details]

Abstract

The principle of this shifter circuit lies on the separation of the 64 bits into eight groups of eight bits each. Shift is performed in going through the two stages of the shifter: Stage 1 : Shifts 0 to 7 groups of 8 bits Stage 2 : Shifts 0 to 7 bits