Transistor Array for Device Defect Diagnostics and Process Control
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
An efficient test structure is described by means of which failing devices can be identified during the measurement of large numbers of transistors. The disclosed test program, which can measure the characteristics of a single device in a matrix of devices, may also be modified to provide a vehicle for establishing device sizes and aspect ratios during planarization process steps.