Browse Prior Art Database

Polysilicon Emitter Sidewall Coverage for Misaligned S-Studs

IP.com Disclosure Number: IPCOM000035950D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28

Publishing Venue

IBM

Related People

Authors:
Bhattacharya, SS Kuhlman, DD Schepis, DJ Lakritz, MN [+details]

Abstract

A process has been developed to avoid Al creep around misaligned studs in semiconductor devices. The deposition of an insulator layer prior to the masking for S-stud lift-off and then the etching of this layer through the lift-off mask causes it to remain in the area adjacent to the stud, thereby providing additional protection against Al penetration.