Synchronous Buffered Maintenance Adapter
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
The adapter provides a means of converting between a standard microprocessor interface and multiple high-speed interfaces into the maintenance hardware of a computer's central processor complex (CPC). It allows a single controlling microprocessor to communicate commands and data with the CPC hardware using minimal resources on either side.