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Logically Controlled Chip Interconnection Technique

IP.com Disclosure Number: IPCOM000035975D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28

Publishing Venue

IBM

Related People

Authors:
Najmann, K Schettler, H van Steenkiste, C Blum, A [+details]

Abstract

A silicon wiring wafer 1 is used as a carrier for chips 2 and as a chip interconnection means (Fig. 1). The interchip wiring consists of a single or a multi-level grid of wire segments 3 (Fig. 2) on the wiring wafer. The wire segments may be implemented as metal conductor strips, polysilicon type material or even as optical links.