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Three-Level Memory Structure for Performance-Oriented Machine Code Placement Disclosure Number: IPCOM000035982D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28

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Related People

Doettling, G Rudolph, P Schulze-Schoelling, H Bock, DW [+details]


The processing unit (PU) supports a control store address space of 64k. Different criteria with regard to performance and accessibility have made it necessary to distribute the microcode in three separate storage media: 1) a high-performance part located in a fast RAM, 2) a medium-performance part located in the main store, and 3) a slow-performance part located in a non-volatile store (EPROM).