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INTEGRATED ERROR Correction/Test MEMORY Feature Disclosure Number: IPCOM000036010D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Document File: 3 page(s) / 37K

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Related People

Najmann, K: AUTHOR [+3]


The feature to which this article refers is described below.

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The feature to which this article refers is described below.

A memory location is accessed by

1. activating a row address by the appropriate control


2. sensing the memory cell data of a row into sense


3. selecting one of the sense latches for data update

(write) and gating out data (read), and

4. restoring the sense latch contents in the

addressed row.

(Image Omitted)

The integrated ECC/test feature for the array is realized by extending the number of columns by the appropriate number of check bits, thus allowing ECC of an addressed row (Fig. 1).

The memory chip can be operated either in the normal or in the test mode. Switching between modes is done by a dedicated signal or in a special sequence, such as Not RAS, CAS, Write, switches to test mode Not RAS, CAS, Not Write, switches to normal mode.

The relevant logical functions for error correction/detection, initialization and self-testing are also integrated on the memory chip (Figs. 2 and 3).

FUNCTIONS OF MEMORY WITH INTEGRATED ECC/TEST FEATURE: The memory chip is accessed like a standard DRAM in the normal mode and performs standard operations, such as read from an address, write into an address, and refresh a row. The integrated logic supports the functions of error correction during the refresh operation (correcting soft errors), initializing the memory chip with "0" and "1", respectively, and self-testing the memory chip with a "pseudo- random" pattern.

ERROR CORRECTION DURING REFRESH: The main advantage of this function is that soft errors are corrected. An ECC syndrome is generated when a row is refreshed. This syndrome indicates any one of the following conditions: no error

correctable error

uncorrectable error