ECC Controller for Memories
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28
Error correction codes (ECCs) for memories are generally designed for 2-bit error detection and 1-bit correction. If applied to 3-bit errors, they would lead to a 1-bit error indication, with the 1-bit correction carried out in response to damaging user data. To avoid this, an ECC controller is proposed.