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Array Card With Partially Good Array Modules

IP.com Disclosure Number: IPCOM000036061D
Original Publication Date: 1989-Aug-01
Included in the Prior Art Database: 2005-Jan-28

Publishing Venue

IBM

Related People

Authors:
Barbash, WA Hardiman, CF [+details]

Abstract

In the design of computer storage, large numbers of array elements (modules) are often interconnected in a two-dimensional (address X I/O) matrix on an array card. In applications where economic factors outweigh density considerations, it can be desirable to use array modules that are imperfect in a predictable manner. One type of partially good module has M addresses by N input/output (I/O) lines, where P out of N I/O lines are "good". Since there are many possible combinations of partially good modules that can occur, the conventional way to make use of these modules is to design a unique array card interconnection pattern for each type of partially good array module.