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Enhanced Planarization Technique

IP.com Disclosure Number: IPCOM000036084D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28

Publishing Venue

IBM

Related People

Authors:
Pickens, MW Stanasolovich, D Theisen, JF [+details]

Abstract

Planarizing resist layers are used to provide for structures to be used in the present generation of planar passivation layers in semiconductor chips. A major shortcoming in these resist systems is that they are not always truly planarizing. This is particularly true in an area of densely clustered structures generating aggressive topography surrounded by an area that contains little or no topography. The planarizing resist layer will often planarize both areas; however, the height of the resist will differ significantly over the two areas. This phenomenon is illustrated in Fig. 1. Any subsequent etch would transfer this height differential into the film which was desired to be planar. Another example is the case of isolated, large recesses in a film or material which is desired to be filled.