Browse Prior Art Database

Third Pipe-Line for a Two Pipe-Line Processor Architecture

IP.com Disclosure Number: IPCOM000036093D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28

Publishing Venue

IBM

Related People

Authors:
Beraud, JP D'Audigier, P [+details]

Abstract

Widely used processors capitalize on a two pipe-line architecture for powerful features such as table look-up, multi-branches and saved address or subroutines [*]. The two pipe-lined cycles perform the instruction fetch followed by the instruction execution. As shown in Fig. 1A, during the fetch, the instruction is taken from the instruction memory and prepared for execution; the decode and the indexation calculation for data memory access are in fact made.