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Fast CMOS Two-Stage Word Decoder

IP.com Disclosure Number: IPCOM000036109D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28

Publishing Venue

IBM

Related People

Authors:
Chao, H Clemen, R [+details]

Abstract

A clocked two-stage CMOS decoder is proposed which requires only two PFET/NFET pairs for the final decoder: a first pair TP1, TN1 to NAND- gate the predecoded select signals WX and WY and a second pair TP2, TN2 to provide sufficient drive capability.