Fast CMOS Output Latch for a Ram
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
A fast CMOS output sense/latch scheme is proposed which provides an adjustable data output hold time and does not require a critical timing edge. This is achieved by using a gated CMOS latch attached to a set/reset-type (main) sense amplifier.