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High Density Wiring Process Disclosure Number: IPCOM000036119D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28

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Stanasolovich, D Theisen, J [+details]


A major obstacle to further increases in the circuit density is the overlay tolerance associated with the alignment of each via level to the previous metal interconnect level. This tolerance and its associated borders consumes a substantial amount of circuit wiring area. In addition, the use of separate photo levels for the vias and the metal interconnects necessitates additional exposure systems, more extensive processing, and a greater yield loss due to defects caused by increased processing. This article discusses a process technology that produces a self-aligned via stud-metal interconnect structure that reduces the problems discussed above.