Dismiss
The InnovationQ application will be updated on Sunday, May 31st from 10am-noon ET. You may experience brief service interruptions during that time.
Browse Prior Art Database

Dual Bus Processor Architecture

IP.com Disclosure Number: IPCOM000036136D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28

Publishing Venue

IBM

Related People

Authors:
Millas, RJ [+details]

Abstract

This article describes a processor system arrangement consisting of a single processor with two sets of data, address and control buses and a separate set of instruction memory buses. The two sets of buses are used to access memory and input/output (I/O) devices located in the same memory map simultaneously.