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Dual Bus Processor Architecture

IP.com Disclosure Number: IPCOM000036136D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28

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Millas, RJ [+details]


This article describes a processor system arrangement consisting of a single processor with two sets of data, address and control buses and a separate set of instruction memory buses. The two sets of buses are used to access memory and input/output (I/O) devices located in the same memory map simultaneously.