Browse Prior Art Database

Interleave Method for Cache Address Lines Disclosure Number: IPCOM000036146D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28

Publishing Venue


Related People

Dixon, JD Keener, DS Voorhees, RW Morel, JE [+details]


This article describes a method which provides for one gate array circuit to interface with a cache random-access memory (RAM) and allows operation with many different sizes of RAM without having to use external pins to select modes of operation of the gate array chip.