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Shift Register Latch for Delay Testing

IP.com Disclosure Number: IPCOM000036167D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28

Publishing Venue

IBM

Related People

Authors:
McAnney, WH [+details]

Abstract

Testing for delay faults requires a pair of patterns, an initialization pattern and a transition pattern. Delay testing in a double-latch LSSD environment, as noted in Section VII of [*], requires that the usual S cycles of A/B shift clocks for a scan string of length S be replaced by S-1 cycles followed by an A clock. This leaves each L1 latch with a value obtained from its predecessor L2, and (obviously) each L2 with the value in its succeeding L1. The L2 values initialize certain paths through the logic. Now pulsing the B clock will shift the L1 value into L2 and hence launch a transition into the logic. This whole process is called 'transition shifting'.