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SRL Modification to Provide Sample Function in Single-Latch Design Disclosure Number: IPCOM000036176D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28

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McAnney, WH [+details]


The Joint Test Action Group (JTAG) boundary scan architecture [*] requires the use of a parallel scannable latch adjacent to each component pin so that signals at component boundaries can be controlled and observed using scan operations. The reason for parallel (rather than series) latches is to permit a concurrent monitoring or sampling of the data flowing across the component boundary (using a scan operation on the boundary latches) without affecting the normal operation of the system. This function is valuable for design debugging and fault diagnosis, and allows the development of system-level maintenance and support functions. (Image Omitted)