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PROCESS FOR LOW RESISTIVITY CoSi2 CONTACT TO VERY SHALLOW N-P JUNCTION

IP.com Disclosure Number: IPCOM000036212D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28

Publishing Venue

IBM

Related People

Authors:
Aboelfotoh, MO d'Heurle, FM Thomas, O Krusin-Elbaum, L [+details]

Abstract

In this disclosure a process for making very low resistivity CoSi2 contact to shallow p-n junction as well as low resistivity CoSi2 FET gate is discussed. Referring to Figs. 1a through 1d, a layer of Co is deposited on n-type substrate through a window defined by an SiO2 layer as shown in Fig. 1a. The structure is then heated at sufficiently high temperature to form CoSi2 . Following the heat treatment process, excess CoS is chemically removed, resulting in the structure shown in Fig. 1b. Boron (B) is implanted into the CoSi2 layer. Energy of the implanted ions is such that the width of the implanted region is 10 to 20% of the total thickness of CoSi2 layer, as shown in Fig. 1c. (Image Omitted)