The following operators can be used to better focus your queries.
( ) , AND, OR, NOT, W/#
? single char wildcard, not at start
* multi char wildcard, not at start
(Cat? OR feline) AND NOT dog?
Cat? W/5 behavior
(Cat? OR feline) AND traits
Cat AND charact*
This guide provides a more detailed description of the syntax that is supported along with examples.
This search box also supports the look-up of an IP.com Digital Signature (also referred to as Fingerprint); enter the 72-, 48-, or 32-character code to retrieve details of the associated file or submission.
Concept Search - What can I type?
For a concept search, you can enter phrases, sentences, or full paragraphs in English. For example, copy and paste the abstract of a patent application or paragraphs from an article.
Concept search eliminates the need for complex Boolean syntax to inform retrieval. Our Semantic Gist engine uses advanced cognitive semantic analysis to extract the meaning of data. This reduces the chances of missing valuable information, that may result from traditional keyword searching.
Disclosed is a fuse adjustable CMOS delay circuit. The circuit can delay the signal when fuse is blown with minimum DC power dissipation. The rising and falling edge can be adjusted separately.
English (United States)
This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately
84% of the total text.
Page 1 of 2
Disclosed is a fuse adjustable CMOS delay circuit. The circuit can delay the
signal when fuse is blown with minimum DC power dissipation. The rising and
falling edge can be adjusted separately.
The key block of the invented delay chain is shown in Fig. 1. There is no
limitation for the number of pairs of inverters between node A and B, but an even
number of inverters must be used. Before the fuse is blown, T1 has nothing to do
with the circuit behavior because both source and drain are grounded. Thus, this
circuit works as a two inverter delay chain. When the fuse is blown, only the
falling edge of the pulse at node C is delayed because of the stacked NMOS
transistors T1 and T2. The soft latch T4 is used to keep node C at 5 V. During
the delay time, T4 will keep node C high in spite of the charge sharing between
the node C and D in this floating period when only T2 is on (T1 is off). The
amount of delay can easily be adjusted by changing the number of inverter
stages or changing W/L in each inverter.
This circuit block can be arranged as is shown in Fig. 2 to make possible 3
different delay timing selections for both rising and falling edges of the input
pulse. The delay block is stacked for both the rising edge and falling edge to
achieve 2, 6, and 10 inverter delays. Therefore, 3 different delays are provided
by a circuit with two fuses. Another alternative of the delay circuit is shown in Fig.
3, which can delay either the rising or...