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This article describes a circuit arrangement which utilizes a latch that is set at power-on time with power-on reset to prevent erroneous microcode changes to the contents of a configuration register.
English (United States)
This text was extracted from a PDF file.
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This is the abbreviated version, containing approximately
54% of the total text.
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Configuration Register and Protection Mechanism
This article describes a circuit arrangement which utilizes a latch that is set
at power-on time with power-on reset to prevent erroneous microcode changes
to the contents of a configuration register.
In computer very large-scale integration (VLSI) hardware design I/O pins may
be held to a zero or one value to affect the characteristics and capabilities of the
design as well as fixed addresses and physical information. The mechanism
disclosed herein replaces a plurality of I/O pins with a shift register which is
loaded when power is first applied.
In operation, after power-on reset has gone inactive, circuitry will generate
shift clocks so that jumper data that is contained in an external shift register can
be loaded into the configuration shift register on the VLSI chip. Varying amounts
of the data may be defaulted to zero or one to reduce the amount of external
hardware. This defaulted portion of the configuration register must then be set by
microcode. Once set, there is no need to change the configuration register
during system operation.
For example, the device address (8 bits) is determined by the card position
that the card is plugged into and therefore this information needs to be entered
from jumpers or switches while the device ID identifies what type of device is
attached and can usually be defaulted and set with microcode since microcode is
generally unique for each device type.
To protect the configuration register from accidental change after
initialization, the protection...