Approach for Fast Interrupt Response in Processors Using Pipeline Architectures
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
An approach is described for improving the interrupt response of signal processors that use pipelined architectures. This is done by using an interrupt state register in the data flow that makes all instruction sequences transparent to interruption. This register, plus a special restore instruction for its control, allows the architecture to avoid the current practice of using interrupt protection on instruction se (Image Omitted) quences. By eliminating protected strings of instructions, the interrupt response is made deterministic, being independent of the program flow, and the minimum interrupt latency is achieved. The approach will be described for a processor having a three-phase pipeline segmented as (INSTRUCTION FETCH), (DECODE/BRANCH) and (EXECUTE).