Cache Comparator Structure Using Write-Over Array
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-28
This disclosure describes an efficient cache comparator structure for a computing system which has virtual memory and uses caches to improve performance. This method of efficient comparison works for instruction caches, data caches, or combined instruction/data caches. The method will be described for a 2-way set associative instruction cache, and a 2-way set associative TLB (Translation Look-aside Buffer), but this method works with any combination of set-associativity for the cache and its TLB.