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This article describes a piece of control logic capable of providing necessary control signals needed to carry a logic self-test operation from start until end without any control over the chip clocks.
English (United States)
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Technique for Implementing Control Logic for Self-Test Operations
This article describes a piece of control logic capable of providing necessary
control signals needed to carry a logic self-test operation from start until end
without any control over the chip clocks.
Consider a chip whose Level Sensitive Scan Design (LSSD)-compatible Shift
Register Latches (SRLs) are configured in a STUMPS (Self- Test Using Multiple
Parallel Signature) Architecture configuration. See Fig. 1.
For the sake of simplicity assume that no arrays exist on the chip and that a
typical self-test event is defined as AB AB AB. . . . . . . . AB CB.
An AB is a term used to describe a scan cycle on the chip. During a scan
cycle a typical SRL receives data through its Scan port. See Fig. 2.
A select signal(s) (also called scan gate) selects between (I) and (D) pins as
data pins to the L1 latch.
The B clock (or L2 clock) transfers data from the output of the L1 latch to the
A CB is a term used to describe a system cycle. During a system cycle the (D) port of the L1 latch is selected and the B clock (or the L2 clock) transfers data
to the L2 latch.
A number of AB cycles is needed to scan data into the whole length of the
longest scan channel. Following that, a CB cycle would capture the chip
response to the scan vector and store it back into the SRLs via the D-ports. To
compress the response data, the scan channel needs to be unloaded (scanned
out) into the Multiple Input Signature Register (MISR), and as the channels are
being unloaded and compressed into the MISR, a new random data vector...