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Five object arrays are interconnected to provide a general-purpose, flexible, extendable content and extendable computer processor architecture. The system has a complete primitive instruction set.
English (United States)
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Logic Model Database Machine Architecture
Five object arrays are interconnected to provide a general-purpose, flexible,
extendable content and extendable computer processor architecture. The
system has a complete primitive instruction set.
To implement data manipulation functions that control the object arrays in a
hardware controller, a memory mapping scheme allows basic calls to read, write
and update model data to be interpreted by an attached processor 10 (see
figure). Common model applications can run on a host system 12, while model
management can run in parallel on the attached processor 10. Shared memory
14 is limited to interfacing areas.
In operation, data is transmitted via shared memory 14; commands and
status are transferred through the attachment mechanism 16. The host
processor 12 notifies the attached processor 10 that it wants service. The
attached processor 10 interprets the command and transfers data between its
model memory 18 and shared storage 14 bidirec tionally. The attached
processor 10 then notifies the host 12 of completion.
To support the common model memory 18 as a view of data between the
attached processor 10 and host processor 12, the attached processor must
partition and suballocate its model memory dynamically among several sets of
model elements. The command interface references model elements, not model
memory locations, by creating an array of memory segment controls and page
controls. Paging space is dynamically allocated fro...