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This addressing method allows a diagonal grid (DG) formatted image to be stored with other more conventional square grid array formatted images. This method requires little additional hardware to support.
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Addressing Method for Diagonal Grid Non-Interlace Raster-Scanned
This addressing method allows a diagonal grid (DG) formatted image to be
stored with other more conventional square grid array formatted images. This
method requires little additional hardware to support.
As designated by the '*' in Fig. 1, all odd counts of the scan
line address require that a row address for memory unit 0 be incremented by
one from the row address for memory unit 1 and that the addresses on all even
counts be the same for both of the memory units.
Fig. 2 shows the additional addressing logic to support the DG addressing
method shown in Fig. 1. Blocks #1 and #2 in Fig. 2 produce conventional
horizontal and vertical timing for a raster scan CRT. Each horizontal blanking
period the scan line address (block #2) is incremented, producing an incremental
count as shown in Fig. 1. During the blanking period the new scan line
information must be loaded into the secondary ports of the video DRAMs. This is
accomplished by a sequence produced from the state machine (block #4) which
is triggered each horizontal sync from the horizontal timer (block #1). The
sequence produced from the state machine causes a special memory cycle (shift
register load cycle).
The address for the shift register load cycle is produce by blocks #2, #3, #5,
#6, #7, #8, #9, and #10. Block #2 drives block #3 with the scan line address.
Block #3 divides the scan line address by two and outputs the dividend and
remainder to blocks #5 and #6. Block #5 increments the address by one. Block
#6 passes the dividend when the remainder equals 0 (even scan line addresses)
or passes the dividend p...