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Disclosed is an interface system by which one serial device can communicate with another serial device of the same clock frequency, but with different clock tolerances and phase relationships.
English (United States)
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Interface Buffer for Connecting Serial Data Communication Subsystems
Disclosed is an interface system by which one serial device can
communicate with another serial device of the same clock frequency, but with
different clock tolerances and phase relationships.
In the serial link design the receiving system is responsible for capturing data
from the serial link. This data is synchronous with the sender's transmit clock.
The receive clock is recovered from the data stream and is generated using a
phase-lock loop generator and is thus subject to unexpected resets, frequency
instability, etc. This generated clock is therefore not suitable to run complex
control logic and state machines at the receiving end. To overcome this problem,
a special-purpose input buffer circuit was designed. This circuit is comprised of
three blocks, as shown in the figure. The first block is synchronized with the
sender and receives the data. The second block is a multi-port register file with
one read and one write port. The third block is synchronized with the receiving
The first block of logic continuously stores the received data in the register
file. Every clock cycle data is written into the register file, and the write address
pointer is incremented by one. At the same time the third block of logic is reading
data from the register file and incrementing the read address pointer each time.
When block 1 detects a start of frame condition, the register file starting addr...