The InnovationQ application will be updated on Sunday, May 31st from 10am-noon ET. You may experience brief service interruptions during that time.
Browse Prior Art Database

Method to Improve Chip Wiring

IP.com Disclosure Number: IPCOM000036383D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-29

Publishing Venue


Related People

Rutter, RS [+details]


Device density and performance of many chips are limited by wiring. If the logic design can be changed to a logically equivalent design that has fewer nets, to certain small, interconnected sets of books, and more nets contained entirely within a set, then a reasonable placement program will be able to produce a better placement for the equivalent design. A method for finding these cases and modifying their design accordingly can reduce wire length to improve density and performance. The method is described in the following. (Image Omitted)