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A technique to allow for AC testing of a Boundary Shift Register Latch (SRL) during logic self-test operations is described.
English (United States)
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Solution to the Problem of AC Self-Test of a Boundary Shift Register Latch
A technique to allow for AC testing of a Boundary Shift Register Latch (SRL)
during logic self-test operations is described.
Overview: This technique allows for AC testing of a Boundary shift register
latch which otherwise could not be possible.
The term AC testing refers to testing the logic under a clock frequency level
comparable to the actual frequency level under which the circuit is intended to
operate. This is possible with chip self- test techniques which are usually
performed at functional speed. However, if the logic level of a particular net does
not change during a self-test operation, then AC testing of a net switching from 1
to 0 and from 0 to 1 is not possible, because, if the transition does not take place
at all, then we would not be able to test if that transition is possible within the
timing limitation of the logic. Therefore, a net transition is necessary and
essential for AC testing during self-test operations.
During self-test operations the 2-way multiplexer (MUX) shown in Fig. 1 must
be controlled in such a way that the receiver (REC) input is deselected and the
Boundary SRL output is selected. This is necessary to prevent contamination of
the final Multiple Input Shift Register signature with an X value latched up into the
Boundary SRL and sourced from the receiver. The problem arises because the
Boundary SRL is latching up its proper output during system cycles, and no
probability exists for testing a 1 to 0 or a 0 to 1 transition through the D input to