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Fault-Tolerant Synchronized Clock Distribution for a Distributed Power System

IP.com Disclosure Number: IPCOM000036407D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-29

Publishing Venue


Related People

Carpenter, BA Shin, CH [+details]


A fault-tolerant synchronized clock distribution technique is disclosed for a distributed power system in order to improve distributed power system noise performance. In order to reduce down time for very large-scale integrated circuit systems due to power failure, redundant power supply systems are desirable. The problem with redundant power supplies is that a centralized power system test and maintenance circuitry generally lack the capability to detect and isolate failures of individual power supplies, so that when one power supply fails, the entire system will enter into a degraded mode and also fail. Fig. 1 shows such a distributed power system wherein one or more line conditioners accept input power and output a 24-volt DC voltage on a power distribution bus to a plurality of DC converters.