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This article discloses a process for avoiding or minimizing in-process corrosion in the power C-4 (controlled-collapse chip connection) connector pads located on MLC (multi-layer ceramic) substrates.
English (United States)
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I/O Pad Design for Preventing In-Process Corrosion of I/O Pads
This article discloses a process for avoiding or minimizing in-process
corrosion in the power C-4 (controlled-collapse chip connection) connector pads
located on MLC (multi-layer ceramic) substrates.
Power C-4 vias are directly connected to the I/O (input/output) pin pads on
the opposite sides of the substrate. The nickel plate on the power C-4 vias, on
the top surface of the MLC substrates, tends to corrode during an immersion
gold-plating step in the current MLC plating process. If so contaminated, e.g., by
nickel oxide or sulfide, gold will begin depositing on the much larger I/O pad,
which is less likely to be covered completely by the contaminant, before
depositing on the power C-4 via. Gold on the I/O pad, in electrical contact with
the, as yet, unplated nickel on the power C-4 via, sets up a galvanic cell, thereby
causing sacrificial corrosion of the nickel.
The disclosed solution to the above problem involves a change in the design
of the I/O pad, electrically isolating the I/O via from the larger surface area of the
pin pad with an annular spacing ring, as shown in the figure. With this change,
the power via 1 coming up to the I/O pad 2 (from the interior of the substrate), is
now separated from the rest of the I/O pad by the annular spacing ring (ceramic
surface) 3. The effect of the difference in size between the power C-4 vias and
the I/O pads is thereby removed, eliminating a primary caus...