Browse Prior Art Database

Scanning a Chip Under the Control of an Asynchronous Slow Clock of a Support Processor

IP.com Disclosure Number: IPCOM000036417D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-29

Publishing Venue

IBM

Related People

Authors:
Jaber, TK [+details]

Abstract

Consider a chip that needs to be scanned out by an external support processor. The support processor has access to a one-scan input pin and a one-scan output pin and is operating on a clock that is slower and asynchronous with respect to the chip clocks. The support processor does not have any control over the chip clocks and needs to scan in/out one and only one bit of data into/from the chip scan strings every time its asynchronous clock completes a clock pulse.