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Unnormalized Number Handling in a Floating-Point Unit

IP.com Disclosure Number: IPCOM000036423D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-29

Publishing Venue

IBM

Related People

Authors:
Cocanougher, D Fry, R [+details]

Abstract

High speed IEEE standard 754 Floating-Point Units (FPUs) must evaluate instructions with very few logic levels. Low cost machines must use smaller numbers of circuits. In both instances the normalization of all numbers from the multiply and add portion of the logic can require large shifters. This invention reduces the number of circuits while also reducing the number of levels required for normalization. The following technique is used: 1. During the full add operation the shift count is created by the Leading Zero Anticipator logic which also reports to the control whether the number can be normalized or not. 2. If the number can not be normalized, the shifter normalizes the number the maximum shift count allowed by the hardware.