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Scan Data Using Common Clocks Across Asynchronous Boundaries Disclosure Number: IPCOM000036432D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-29

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Bansal, A Jaber, TK Ripley, JR [+details]


Disclosed is a process that allows a common processor to control multiple logic partitions which operate on asynchronous clocks. The process allows the common processor to halt the logic partitions without destroying the current latch states, to read or write the latches via LSSD * scan paths, and restart the logic partitions. Keys to Operation_ Fig. 1 shows a block diagram of the logic configuration. A. The clocks provided to the asynchronous partitions must be multiplexed with the common controller's clock. B. The logic partition must be stopped synchronously to the clock which it is currently operating on in order to preserve the latch data. C. The multiplexer which selects the Halt signal must not glitch when the clock multiplexer (Mux) is being switched.