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Algorithm to Communicate Topology and Time Between Circuit and Blocks During TEST Generation

IP.com Disclosure Number: IPCOM000036444D
Original Publication Date: 1989-Sep-01
Included in the Prior Art Database: 2005-Jan-29

Publishing Venue

IBM

Related People

Authors:
Shearon, PC [+details]

Abstract

In a test generator whose flexibility requires the circuit and its blocks to be independent, but where the block assignments of logic values depend on the circuit topology and time, some method must be employed to communicate this information between the circuit and its (Image Omitted) blocks. The following algorithm solved that problem in the test generator ETG.