Logic Reduction for a Hardware Simulator
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
This disclosure presents an algorithm that given an arbitrary AO (AND- OR) block will construct an equivalent logic network subject to the following constraints: 1) The network must consist of a minimal set of logic blocks. 2) Each logic block must have 4 inputs (unused inputs are connected to a constant 0 or constant 1). 3) Any boolean function is acceptable for a logic block.