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Disclosed is an in-page only instruction prefetcher for a CPU complex that is designed to decrease the physical space required to implement an instruction prefetcher with minimal performance impact.
English (United States)
This text was extracted from a PDF file.
This is the abbreviated version, containing approximately
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CPU In-Page Only Instruction Prefetcher
Disclosed is an in-page only instruction prefetcher for a CPU complex that is
designed to decrease the physical space required to implement an instruction
prefetcher with minimal performance impact.
In a 32-bit address and data processor, the address range to prefetch an
instruction is 2 to the power of 32, i.e., 32 signals. The normal way to build an
instruction prefetcher is to design logic that can generate 32-bit addresses. This
typically requires 32-bit adders, 32-bit multiplexers, 32-bit registers, and 32-bit
incrementers throughout the design, a significant amount of hardware.
Where physical space is limited, one can design an In-Page Only Instruction
Prefetcher. The concept is to maximize the characteristic of programs to execute
in the same address range for long periods of time. This address range can differ
from design to design but, in this text, a 4 KB range, or page, will be used, for
example (2 to the power of 12). By designing a instruction prefetcher that only
operates within a page, only 12-bit multiplexers, registers, adders, and
incrementers are required.
A small amount of hardware is required to "fix" the page crossings that will
take place. First, whenever a page crossing is detected in the prefetcher it halts.
This page crossing might be due to the address sequentially incrementing across
the page boundary or from the target address of a branch instruction. These
page crossings require 32-bit hardware...