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Dual Digital Signal Processor Instruction TRACE Mechanism Disclosure Number: IPCOM000036500D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29
Document File: 6 page(s) / 70K

Publishing Venue


Related People

Davis, GT: AUTHOR [+4]


This article describes a technique for tracing of code of two digital signal processors on a card without the involvement of external hardware devices.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 25% of the total text.

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Dual Digital Signal Processor Instruction TRACE Mechanism

This article describes a technique for tracing of code of two digital signal processors on a card without the involvement of external hardware devices.

Disclosed here is a dual digital signal processor instruction trace mechanism (DDSPITM) which is intended for use by digital signal processor (DSP) microcoders wishing to trace DSP code on a dual DSP based card. Access to the DDSPITM is performed by a Motorola 68000- based controller card. Access to the trace buffer and trace controls is accomplished through the 68000 reads and writes.

The DDSPITM traces only microcode branches and interrupts. This is done to optimize the 64x15 trace RAM. Tracing branches rather than actual program flow permits a larger trace to be performed within the limits of the 64 word buffer. The trace RAM is 15 bits wide, 14 bits are for storing the branch addresses, and the remaining bit is used to indicate an actual jump.

(Image Omitted)

The following list sets forth the basic features of the

Trace DSP code on-card.

Traces only instruction flow without direct memory access (DMA) interference.

Trace either DSP1 or DSP2.

Trace only branches.

Trace before or after trigger.

Support multiple triggers.

Support external triggering.


Single step.

Clear Trace RAM.

Clear trace pointer (set +EN=0).

Set breakpoint by setting most significant bit (MSB) of instruction located at the desired breakpoint address.

Set trace control register with desired options and enable (+EN=1).

Begin code execution.

Clearing the trace RAM is performed by having the 68000 write zeros in all 64 trace RAM locations. To clear the trace pointer 0 must be written into the +EN bit of the address trace control register. Trace pointer must be cleared before a trace begins. Setting breakpoint(s) and, trace options is explained later.

OBTAINING TRACE RESULTS: Monitor end of trace (EOT) bit. Trace is complete when EOT is set:


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Read trace pointer.

Read contents from trace RAM.

Follow jump path to determine microcode flow.

If is DSP halted, resume by setting 'Reset IRAM DMA Latch'.

Monitoring the EOT bit is done by having the 68000 read the 68k I/O command/status register, bit 14. To read the trace pointer, the 68000 must read the address trace control register. Bits 0 through 5 of this register will display the trace pointer. Reading the contents of trace RAM depends on what trace mode was performed.

If a trace before trigger (+TA/-TB=0) is selected, the DDSPITM is tracing continuously and wrapping around until a breakpoint is encountered. In this case, the value of the pointer is used to determine where the breakpoint occurred. Then, by reading 64 locations encountered prior to the breakpoint, a valid trace dump is produced, the only exception being that the trace RAM was not full when the breakpoint was encountered. If this happens, only the locations encountered prior to the...