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This article describes a high-speed channel data and address buffer which may be connected to control and memory hardware in a computer system to allow high-speed channel transfers.
English (United States)
This text was extracted from a PDF file.
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58% of the total text.
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High-Speed Channel Data Transfer Logic
This article describes a high-speed channel data and address buffer which
may be connected to control and memory hardware in a computer system to
allow high-speed channel transfers.
In the design of channel attachment hardware additional logic may be
provided to increase channel transfer rates.
Referring to the drawings, Fig. 1 shows the channel attachment function.
The conversion of this function to a single-chip design that operates with
microprocessors with a 16-bit bidirectional data bus requires modification of the
function. Fig. 2 shows the signal input/output (I/O) pins for the single-chip
In the technique disclosed herein a high-speed data transfer function works in
conjunction with external control logic and places no restrictions on possible
external memory configurations or the microprocessor type. The dashed lines in
Fig. 2 show the connections added between the computer and microprocessor
buses. To implement the high- speed data transfer required, the addition of two
signal I/O pins is made to cause the data to flow from left to right (computer to
microprocessor) or from right to left. The third signal between the
transfer logic and the external control logic is used to indicate that the computer
address bus 8-15 compares with the device address. With this information the
external control logic can determine when a high speed data transfer is required.