Browse Prior Art Database

Use of Transparent Shift Register Latches in LSSD Circuit Designs Disclosure Number: IPCOM000036511D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29

Publishing Venue


Related People

Leininger, JC [+details]


This article describes a circuit arrangement wherein a transparent level-sensitive scan design shift register latch is added in LSSD circuit designs to prevent LSSD and testability. (Image Omitted)