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Use of Transparent Shift Register Latches in LSSD Circuit Designs

IP.com Disclosure Number: IPCOM000036511D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29

Publishing Venue

IBM

Related People

Authors:
Leininger, JC [+details]

Abstract

This article describes a circuit arrangement wherein a transparent level-sensitive scan design shift register latch is added in LSSD circuit designs to prevent LSSD and testability. (Image Omitted)