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This article describes a circuit arrangement wherein a transparent level-sensitive scan design shift register latch is added in LSSD circuit designs to prevent LSSD and testability. (Image Omitted)
English (United States)
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Use of Transparent Shift Register Latches in LSSD Circuit Designs
This article describes a circuit arrangement wherein a transparent level-
sensitive scan design shift register latch is added in LSSD circuit designs to
prevent LSSD and testability.
In the design of very large-scale integration (VLSI) components using LSSD
design rules, certain design practices may violate LSSD rules or may be
untestable. Fig. 1 shows a clock generation circuit, a pulse generation circuit and
a pulse widening circuit which are untestable and violate LSSD design rules.
The pulse generator will cause incorrect test patterns to be generated and give
Because there are dual paths in each design, if one path is always at a zero
or a one value, the design may operate satisfactorily under test conditions but it
may foul during system operation or under adverse field conditions due to pulses
being too narrow or two pulses may overlap. Fig. 2 shows how the use of
transparent latches will make the functions in Fig. 1 completely testable.
The transparent latches are created by using standard shift register latches
where the B and C system clocks are always active during system operation so
that data always flushes through the latches.
The pulse generator is untestable since the output state is unchanged after
the input transition when sampled by the tester a relatively long time after the
input transition even though the pulse formed may set or reset a latch, etc.
Because it gives false test results (zero yield), the pulse generator may not be
used as shown in Fig. 1.