Browse Prior Art Database

XCU for Closely Shared L2 Lines Disclosure Number: IPCOM000036516D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29

Publishing Venue


Related People

Emma, PG Knight, JW Pomerene, JH Puzak, TR Rechtschaffen, RN [+details]


In a multiprocessor configuration which is supported by a memory hierarchy involving a Write Through Write Allocate Exclusive (WTWAX) L1 cache per processor and two private Write Back (WB) L2 caches (which may be shared by multiple L1s), the Cross Interrogate (XI) represents a major factor in multiprocessor performance degradation.