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This article describes a pulse-set register circuit which allows an asynchronous setting register to be read and reset at the same time by a microprocessor.
English (United States)
This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately
69% of the total text.
Page 1 of 2
Foolproof Event-Catching Register Circuit
This article describes a pulse-set register circuit which allows an
asynchronous setting register to be read and reset at the same time by a
Typically, the problem arises as to how to deal with an event occurring at the
same time that the register is being read. An automatic "Read-Reset" operation
must not prevent the event from being recorded. This results in one of two
scenarios as follows:
1. If that event is not passed on to the data bus, it must be latched by the
pulse-set register. It must not be affected by the automatic reset action that
occurs when the register is read. If it is, this would result in the event being
missed by the processor.
2. If the event is passed on to the data bus during the current read cycle, the
processor will see it and act accordingly. In this case, the event must not be
latched, or else on a subsequent read, the processor would see the event again,
even though it had occurred only once.
The circuit disclosed herein will work regardless of the time relationship
between the event and the read cycle and will never cause an event to be
missed or read twice.
Fig. 1 shows the pulse-set register circuit of this disclosure. Figs. 2 and 3 are
timing diagrams for the circuit operation. A negative pulse indicates that an
event occurred. The read is also a negative-going pulse, and the data is latched
on the trailing edge of that pulse. In the first example (Fig. 2),...