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Memory management units contain embedded arrays storing virtual and real addresses. The data of these array macros is compared with external addresses DI.
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Integrated Compare for Address Translation
Memory management units contain embedded arrays storing virtual and real
addresses. The data of these array macros is compared with external addresses
The compares consisting of, e.g., 19 bits, one of which is shown in the figure,
may be integrated in clocked address macros. The compare logic is directly
driven by sense amplifier outputs SAT, SAC. A new clocked high-speed XOR
replaces conventional CMOS XORs and ANDs. Output compare line CL of the
19-bit compare is a DOT AND rather than a CMOS AND.
Write head WH generates the true/complement DT, DC of external data DI.
SSAT and SSAC, derived from the set sense amplifier clock, are
true/complement clocks switching at the same time. Prior to sensing and
compare, node XO may be up or down. The novel bus line BUS, if up, avoids a
discharge of CL. Isolation FETs T6, T7 prevent a short in the XOR. CL is
discharged during compare if there is a mismatch between the sense amplifier
(outputs SAT, SAC) and the write head WH (outputs DT, DC).
The line bus clock BUS allows section testing the 19-bit compare.
The compare layout (write head and XOR) matches the pitch of the sense
amplifier and the memory cell, so that a pitch match (structured) design is
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