Browse Prior Art Database

Trace Buffering System for Parallel Simulation of MP Systems

IP.com Disclosure Number: IPCOM000036658D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29

Publishing Venue

IBM

Related People

Authors:
Darema-Rogers, F George, DA Melton, EA Norton, VA Pfister, GF So, K [+details]

Abstract

Simulation at the instruction level of the execution of each CPU in a multiprocessor (MP) system is not just time consuming but is also very I/O intensive. One problem is where and how to efficiently store the huge volume of traces generated so that the whole simulation is not significantly delayed by the trace-writing step. This I/O demand from the base system grows at least linearly with the number of CPUs in the simulated MP system. A Trace Buffering System (TBS) is described below which frees the simulation from the number of I/O devices available and at the same time minimizes any I/O overheads during trace generation. For reasons of high volume and portability, tape is so far the only candidate to store traces of practical length. Therefore, it will be assumed that only tapes are used to store the traces.