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Multiplier With Inverted or Buffered Columns

IP.com Disclosure Number: IPCOM000036674D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29

Publishing Venue

IBM

Related People

Authors:
Dao-Trong, S Fischer, W Helwig, K [+details]

Abstract

In a multiplier comprising lines receiving one operand and columns receiving another operand, the signals in the columns, having passed a number of lines, are inverted or buffered. If a column comprises a true and a complement signal, both signals are inverted or buffered after the same number of lines. In this way, only a small number of multiplier circuits switch simultaneously, reducing the amount of current noise.