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Method for Simulating a Latch-Trigger Logic Design Disclosure Number: IPCOM000036694D
Original Publication Date: 1989-Oct-01
Included in the Prior Art Database: 2005-Jan-29

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Buonomo, JM [+details]


A typical implementation of a latch-trigger logic circuit requires two latches (L1 and L2) for each SRL in the circuit. Two non-overlapping clocks (C1 and C2) are required throughout the device to clock the pairs of latches, as shown in Fig. 1.